Verilog小电路除法器设计

module Non_restoring_Divider
#(parameter N = 4)
(
	input 	   [2 * N-2:0] dividend_i,
	input 	   [N-1:0] divisor_i,
	output  [N-1:0] quotient_o,
	output  [2 * N-2:0] remainder_o
);

genvar i;

// reg  [2 * N-2:0] tempR [N:0];
logic  [2 * N-2:0] tempR [N:0];
assign tempR[0] = dividend_i;
assign tempR[1] = tempR[0] - (divisor_i << (N-1));
assign quotient_o[N-1] = (tempR[1][2 * N-2-1] == 1'b1) ? 0 : 1;

generate
for (i=2; i <= N; i=i+1) begin:shift_and_calculate_result
	assign tempR[i] = tempR[i-1][2 * N-2-1] == 1 ? (tempR[i-1] + (divisor_i << (N-i))) : (tempR[i-1] - (divisor_i << (N-i)));
	assign quotient_o[N-i] = tempR[i][2 * N-2-1] == 1 ? 0 : 1;
end
endgenerate

	assign remainder_o = tempR[N] + (1 - quotient_o[0]) * divisor_i;
endmodule

Verilator:

#include "verilated_vcd_c.h" //可选，如果要导出vcd则需要加上
#include "VNon_restoring_Divider.h"
 
vluint64_t main_time = 0;  //initial 仿真时间
 VNon_restoring_Divider *top = new VNon_restoring_Divider("top"); //调用VNon_restoring_Divider.h里面的IO struct
double sc_time_stamp()
{
    return main_time;
}

int main(int argc, char **argv)
{
    Verilated::commandArgs(argc, argv); 
    Verilated::traceEverOn(true); //导出vcd波形需要加此语句
 
    VerilatedVcdC* tfp = new VerilatedVcdC; //导出vcd波形需要加此语句
    top->trace(tfp, 0);   
    tfp->open("wave2.vcd"); //打开vcd
    while (sc_time_stamp() < 5 && !Verilated::gotFinish()) { //控制仿真时间
        top->dividend_i = 15 + sc_time_stamp();
        top->divisor_i = 3;
        top->eval(); //计算输出
        printf("Quotient:%d Remainder:%d\n", top->quotient_o, top->remainder_o);
        tfp->dump(main_time); //dump wave
        main_time++; //推动仿真时间
    }
    top->final();
    tfp->close();
    delete top;
 
    return 0;
}

Makefile

all:
	@echo "Write this Makefile by your self."
	verilator -Wno-fatal Non_restoring_Divider.v main.c --top-module Non_restoring_Divider --cc --trace --exe
	make -C obj_dir -f VNon_restoring_Divider.mk VNon_restoring_Divider
	./obj_dir/VNon_restoring_Divider