RISC-V特权指令集CSR寄存器初探

前提知识

• CSR[11:0] encoding space
• CSR[11:8] 解码 读写
• non-existent CSR raise an illegal instruction exception.
• Attempts to access a
  CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
• A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored

确定需要基本支持的寄存器

以下寄存器在NutShell中均进行实现

S Mode

1. Sstatus    2. Sedeleg    3. Sideleg   4. Sie
2. Stvec      6. Scounteren 7. Sscratch  8. Sepc
3. Scause     10. Stval     11. Sip      12. Satp

M Mode

1. Mvendorid  2. Marchid    3. Mimpid    4. Mhartid
2. Mstatus    6. Misa       7. Medeleg   8.Mideleg    
3. Mie        10. Mtvec     11. Mcounteren
4. Mscratch  13. Mepc      14. Mcause   15. Mtval
5. Mip

从M部分寄存器讲起

WARL

P12
原文：
Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read. Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained. These fields are labeled WARL in the register descriptions.

Implementations will not raise an exception on writes of unsupported values to a WARL field. Implementations can return any legal value on the read of a WARL field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.

Machine ISA Register(misa)

Volume2, P32
用于当前支持的RISC-V子集的配置信息

Machine Vendor ID Register(mvendorid)

产品供应商的ID，可以设置非商用

Machine Implementation ID Register(mimpid)

提供处理器实现版本的唯一编码

Hart ID Register(mhartid)

硬件级线程区分相关
关于Hart缩写的解释：
HARdware Thread
详见：https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjUDjz_vKo